HD6473847RHV Datasheet, PDF (117/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 3 Exception Handling
IRQAEC Interrupt
The IRQAEC interrupt is requested by an input signal to pin IRQAEC. This interrupt is detected
by either rising edge sensing or falling edge sensing, depending on the settings of bits AIEGS1
and AIEGS0 in AEGSR.
When bit IENEC2 in IENR1 is designated for interrupt input and the designated signal edge is
input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt.
Reset cleared
Initial program
Vector fetch Internal ^{instruction prefetch}
processing
φ
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
(1)
(2)
(2)
(3)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
Figure 3.1 Reset Sequence
3.4.2 Internal Interrupts
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to
enable or disable the interrupt. For direct transition interrupt requests generated by execution of a
SLEEP instruction, this function is included in IRR1 and IRR2.
When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit
Rev. 7.00 Mar. 08, 2010 Page 85 of 510
REJ09B0024-0700