HD6473847RHV Datasheet, PDF (330/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 10 Serial Communication Interface 3 (SCI3)
Table 10.12 Transmit/Receive Interrupts
Interrupt
RXI
TXI
TEI
Flag and
Enable
Bit
Interrupt Request Conditions
Notes
RDRF
RIE
When serial reception is performed The RXI interrupt routine reads the
normally and receive data is
receive data transferred to RDR
transferred from RSR to RDR, bit
and clears bit RDRF to 0.
RDRF is set to 1, and if bit RIE is set Continuous reception can be
to 1 at this time, RXI is enabled and an performed by repeating the above
interrupt is requested. (See figure
operations until reception of the
10.15(a).)
next RSR data is completed.
TDRE
TIE
When TSR is found to be empty (on
completion of the previous
transmission) and the transmit data
placed in TDR is transferred to TSR,
bit TDRE is set to 1. If bit TIE is set to
1 at this time, TXI is enabled and an
interrupt is requested. (See figure
10.15(b).)
The TXI interrupt routine writes the
next transmit data to TDR and
clears bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations
until the data transferred to TSR
has been transmitted.
TEND
TEIE
When the last bit of the character in TEI indicates that the next transmit
TSR is transmitted, if bit TDRE is set data has not been written to TDR
to 1, bit TEND is set to 1. If bit TEIE is when the last bit of the transmit
set to 1 at this time, TEI is enabled character in TSR is transmitted.
and an interrupt is requested. (See
figure 10.15(c).)
RDR
RDR
RXD32 pin
RSR (reception in progress)
RXD32 pin
RSR↑ (reception completed, transfer)
RDRF = 0
RDRF 1
(RXI request when RIE = 1)
Figure 10.15(a) RDRF Setting and RXI Interrupt
Rev. 7.00 Mar. 08, 2010 Page 298 of 510
REJ09B0024-0700