HD6473847RHV Datasheet, PDF (305/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 10 Serial Communication Interface 3 (SCI3)
Table 10.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
φ
2 MHz
5 MHz
8 MHz
Bit Rate
Error
(bit/s)
n N (%)
nN
Error
(%)
nN
Error
(%)
110
3 8 –1.36 3 21 0.88
3 35 –1.36
150
2 25 0.16 3 15 1.73
3 25 0.16
200
3 4 –2.34 3 11 1.73
3 19 –2.34
250
2 15 –2.34 3 9 –2.34 3 15 –2.34
300
2 12 0.16 3 7 1.73
3 12 0.16
600
0 103 0.16 3 3 1.73
2 25 0.16
1200
0 51 0.16 3 1 1.73
2 12 0.16
2400
0 25 0.16 3 0 1.73
0 103 0.16
4800
0 12 0.16 2 1 1.73
0 51 0.16
9600
———
20
1.73
0 25 0.16
19200
———
07
1.73
0 12 0.16
31250
010
04 0
07
0
38400
———
0 3 1.73
—— —
Legend:
No indication: Setting not possible.
⎯:
A setting is available but error occurs
10 MHz
Error
n N (%)
3 43 0.88
3 32 –1.36
3 23 1.73
3 19 –2.34
3 15 1.73
3 7 1.73
3 3 1.73
3 1 1.73
3 0 1.73
2 1 1.73
2 0 1.73
090
0 7 1.73
Table 10.3 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
0
φ /2^*1/φ ^*2
0
1
W
W
2
φ/16
1
0
3
φ/64
1
1
Notes: 1. φ_W/2 clock in active (medium-speed/high-speed) mode and sleep (medium-speed/high-
speed) mode
2. φ_W clock in subactive mode and subsleep mode
In subactive or subsleep mode, the SCI3 can be operated when CPU clock is φ_W/2 only.
Rev. 7.00 Mar. 08, 2010 Page 273 of 510
REJ09B0024-0700