HD6473847RHV Datasheet, PDF (75/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 2 CPU
2.5.2 Arithmetic Operations Instructions
Table 2.4 describes the arithmetic operations instructions.
Table 2.4 Arithmetic Operations Instructions
Instruction Size^* Function
ADD
SUB
B/W Rd ± Rs → Rd, Rd + #IMM → Rd
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data can
be added or subtracted only when both words are in general registers.
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data in two general
registers, or addition or subtraction with carry on immediate data and
data in a general register.
INC
DEC
B
Rd ± 1 → Rd
Increments or decrements a general register by 1.
ADDS
SUBS
W
Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts 1 or 2 to or from a general register.
DAA
DAS
B
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU
B
Rd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result.
DIVXU
B
Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder.
CMP
B/W Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets CCR bits according to the result. Word
data can be compared only between two general registers.
NEG
B
0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register.
Note: * Refers to the operand size.
B: Byte
W: Word
Rev. 7.00 Mar. 08, 2010 Page 43 of 510
REJ09B0024-0700