HD6473847RHV Datasheet, PDF (300/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 10 Serial Communication Interface 3 (SCI3)
10.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. SSR is
initialized to H'84 at a reset and in standby, watch, or module standby mode.
Initial
Bit
Bit Name Value R/W Description
7
TDRE
1
R/(W)^* Transmit Data Register Empty
Indicates that transmit data is stored in TDR.
[Setting conditions]
• When the TE bit in SCR3 is 0
• When data is transferred from TDR to TSR
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
6
RDRF
0
• When the transmit data is written to TDR
R/(W)^* Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
• When serial reception ends normally and receive data
is transferred from RSR to RDR
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When data is read from RDR
If an error is detected in reception, or if the RE bit in
SCR3 has been cleared to 0, RDR and bit RDRF are not
affected and retain their previous state.
Note that if data reception is completed while bit RDRF is
still set to 1, an overrun error (OER) will occur and the
receive data will be lost.
Rev. 7.00 Mar. 08, 2010 Page 268 of 510
REJ09B0024-0700