HD6473847RHV Datasheet, PDF (67/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 2 CPU
2.3.3 Condition Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I),
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1
by reset exception-handling sequence, but other bits are not initialized.
Initial
Bit
Bit Name Value
R/W Description
7
I
1
R/W Interrupt Mask Bit
Masks interrupts when set to 1. The I bit is set to 1 at
the start of an exception-handling sequence.
6
U
Undefined R/W User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
5
H
Undefined R/W Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, or CMP.W
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and cleared to 0 otherwise.
4
U
Undefined R/W User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
3
N
Undefined R/W Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2
Z
Undefined R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1
V
Undefined R/W Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
Rev. 7.00 Mar. 08, 2010 Page 35 of 510
REJ09B0024-0700