HD6473847RHV Datasheet, PDF (314/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 10 Serial Communication Interface 3 (SCI3)
10.4.2 SCI3 Initialization
Follow the flowchart as shown in figure 10.4 to initialize the SCI3. When the TE bit is cleared to
0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of
the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in
asynchronous mode, the clock must be supplied even during initialization. When the external
clock is used in clocked synchronous mode, the clock must not be supplied during initialization.
Start initialization
Clear TE and RE bits in SCR3 to 0
[1]
Set CKE1 and CKE0 bits in SCR3
Set data transfer format in SMR
[2]
Set value in BRR
[3]
Wait
No
1-bit interval elapsed?
Yes
Set SPC32 bit in SPCR to 1
[4]
Set TE and RE bits in
SCR3 to 1, and set RIE, TIE, TEIE,
and MPIE bits.
<Initialization completion>
[1] Set the clock selection in SCR3.
Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
When the clock output is selected in
asynchronous mode, clock is output
immediately after CKE1 and CKE0
settings are made. When the clock
output is selected at reception in clocked
synchronous mode, clock is output
immediately after CKE1, CKE0, and RE
are set to 1.
[2] Set the data transfer format in SMR.
[3] Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4] Wait at least one bit interval, then set the
TE bit or RE bit in SCR3 to 1. Setting
bits TE and RE enables the TXD32 and
RXD32 pins to be used. Also set the
RIE, TIE, TEIE, and MPIE bits,
depending on whether interrupts are
required. In asynchronous mode, the bits
are marked at transmission and idled at
reception to wait for the start bit.
Figure 10.4 Sample SCI3 Initialization Flowchart
Rev. 7.00 Mar. 08, 2010 Page 282 of 510
REJ09B0024-0700