HD6473847RHV Datasheet, PDF (114/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 3 Exception Handling
Bit
0
Note:
Initial
Bit Name Value R/W Description
IRREC 0
R/W^* Asynchronous Event Counter Interrupt Request Flag
[Setting condition]
When ECH overflows in 16-bit counter mode, or ECH or
ECL overflows in 8-bit counter mode
[Clearing condition]
When IRREC = 1, it is cleared by writing 0
* Only 0 can be written for flag clearing.
3.2.6 Wakeup Interrupt Request Register (IWPR)
IWPR is a status flag register for WKP7 to WKP0 interrupt requests. The flags are not cleared
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Initial
Bit
Bit Name Value R/W Description
7
IWPF7 0
R/W^* Wakeup Interrupt Request Flag 7 to 0
6
IWPF6 0
R/W^* [Setting condition]
5
IWPF5 0
4
IWPF4 0
3
IWPF3 0
2
IWPF2 0
1
IWPF1 0
R/W^*
R/W^*
R/W^*
R/W^*
R/W^*
When pin WKPn is designated for wakeup input and the
designated edge is detected
(n = 7 to 0)
[Clearing condition]
When IWPFn= 1, it is cleared by writing 0
0
IWPF0 0
R/W^*
Note: * Only 0 can be written for flag clearing.
Rev. 7.00 Mar. 08, 2010 Page 82 of 510
REJ09B0024-0700