HD6473847RHV Datasheet, PDF (298/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 10 Serial Communication Interface 3 (SCI3)
10.3.6 Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to select the transfer clock source. SCR3 is initialized to H'00 at a reset and in standby,
watch, or module standby mode. For details on interrupt requests, refer to section 10.7, Interrupts.
Initial
Bit
Bit Name Value R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled. TXI can be released by clearing the TDRE bit or
TIE bit to 0.
6
RIE
0
R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled. RXI and ERI can be released by clearing bit
RDRF or the FER, PER, or OER error flag to 0, or by
clearing bit RIE to 0.
5
TE
0
R/W Transmit Enable
When this bit is set to 1, transmission is enabled. When
this bit is 0, the TDRE bit in SSR is fixed at 1. When
transmit data is written to TDR while this bit is 1, bit
TDRE in SSR is cleared to 0 and serial data transmission
is started. Be sure to carry out SMR settings, and setting
of bit SPC32 in SPCR, to decide the transmission format
before setting bit TE to 1.
4
RE
0
R/W Receive Enable
When this bit is set to 1, reception is enabled. In this
state, serial data reception is started when a start bit is
detected in asynchronous mode or serial clock input is
detected in clocked synchronous mode. Be sure to carry
out the SMR settings to decide the reception format
before setting bit RE to 1.
Note that the RDRF, FER, PER, and OER flags in SSR
are not affected when bit RE is cleared to 0, and retain
their previous state.
3
MPIE
0
R/W Reserved
It's a reserved bit.
Rev. 7.00 Mar. 08, 2010 Page 266 of 510
REJ09B0024-0700