HD6473847RHV Datasheet, PDF(162/546 Page) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

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HD6473847RHV Datasheet, PDF (162/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

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Section 5 Power-Down Modes

5.4 Module Standby Function

The module-standby function can be set to any peripheral module. In module standby mode, the

clock supply to modules stops to enter the power-down mode. Module standby mode enables each

on-chip peripheral module to enter the standby state by clearing a bit that corresponds to each

module in CKSTPR1 and CKSTPR2 to 0 and cancels the mode by setting the bit to 1. (See section

5.1.3, Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2).)

5.5 Usage Notes

5.5.1 Standby Mode Transition and Pin States

When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)

mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is

cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the high-

impedance state (except pins for which the pull-up MOS is designated as on). Figure 5.2 shows

the timing in this case.

Ï

Internal data bus

Pins

SLEEP instruction fetch Next instruction fetch

SLEEP instruction execution Internal processing

Port output

High-impedance

Active (high-speed) mode or active (medium-speed) mode

Standby mode

Figure 5.2 Standby Mode Transition and Pin States

5.5.2 Notes on External Input Signal Changes before/after Standby Mode

1. When external input signal changes before/after standby mode or watch mode

When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and

low-level widths of the signal must be at least two cycles of system clock Ï or subclock ÏSUB

(referred to together in this section as the internal clock). As the internal clock stops in standby

mode and watch mode, the width of external input signals requires careful attention when a

transition is made via these operating modes. Ensure that external input signals conform to the

conditions stated in 3, Recommended timing of external input signals, below.

Rev. 7.00 Mar. 08, 2010 Page 130 of 510

REJ09B0024-0700

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