HD6473847RHV Datasheet, PDF (144/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 5 Power-Down Modes
5.1 Register Descriptions
The registers related to power-down modes are as follows.
• System control register 1 (SYSCR1)
• System control register 2 (SYSCR2)
• Clock halt registers 1 and 2 (CKSTPR1 and CKSTPR2)
5.1.1 System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Initial
Bit
Bit Name Value R/W Description
7
SSBY
0
R/W Software Standby
Selects the mode to transit after the execution of the
SLEEP instruction.
0: A transition is made to sleep mode or subsleep mode.
1: A transition is made to standby mode or watch mode.
For details, see table 5.2.
6
STS2
0
R/W Standby Timer Select 2 to 0
5
STS1
0
4
STS0
0
R/W Designate the time the CPU and peripheral modules wait
R/W ^{for stable clock operation after exiting from standby}
mode, subactive mode, subsleep mode, or watch mode
to active mode or sleep mode due to an interrupt. The
designation should be made according to the operating
frequency so that the waiting time is at least equal to the
oscillation stabilization time. The relationship between the
specified value and the number of wait states is shown in
tables 5.1(1) and 5.1(2).
When an external clock is to be used, the minimum value
(STS2 = 1, STS1 = 0, STS0 = 1) is recommended. 8,192
states (STS2 = STS1 = STS0 = 0) is recommended if the
on-chip oscillator is used on the H8/38104 Group. If the
setting other than the recommended value is made, op-
eration may start before the end of the waiting time.
3
LSON
0
R/W Selects the system clock (φ) or subclock (φ ) as the
SUB
CPU operating clock when watch mode is cleared.
0: The CPU operates on the system clock (φ)
1: The CPU operates on the subclock (φ )
SUB
Rev. 7.00 Mar. 08, 2010 Page 112 of 510
REJ09B0024-0700