English
Language : 

HD6473847RHV Datasheet, PDF (86/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series
Section 2 CPU
Register Indirect—@Rn
The register field of the instruction specifies a 16-bit general register containing the address of the
operand in memory.
Register Indirect with Displacement—@(d:16, Rn)
The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the
contents of the specified general register (16 bits) to obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address
must be even.
Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @-Rn
• Register indirect with post-increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
The register field of the instruction specifies a 16-bit general register containing the address of
the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for
MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
• Register indirect with pre-decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
The register field of the instruction specifies a 16-bit general register which is decremented by
1 or 2 to obtain the address of the operand in memory. The register retains the decremented
value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original
contents of the register must be even.
Absolute Address—@aa:8/@aa:16
The instruction specifies the absolute address of the operand in memory.
The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit
manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR
instructions can use 16-bit absolute addresses.
For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is
H'FF00 to H'FFFF (65280 to 65535).
Rev. 7.00 Mar. 08, 2010 Page 54 of 510
REJ09B0024-0700