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HD6473847RHV Datasheet, PDF (282/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series
Section 9 Timers
9.4.5 Operating States of Asynchronous Event Counter
The operating states of the asynchronous event counter are shown in table 9.7.
Table 9.7 Operating States of Asynchronous Event Counter
Operating
Mode
Reset Active
Sleep
Watch
Sub-
active
Sub-sleep Standby
Module
Standby
AEGSR
ECCR
ECCSR
ECH
ECL
IRQAEC
Reset
Reset
Reset
Reset
Reset
Reset
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Retained*1 Functions Functions Retained*1
Retained*1 Functions Functions Retained*1
Retained*1 Functions Functions Retained*1
Functions*1*2 Functions*2 Functions*2 Functions*1*2
Functions*1*2 Functions*2 Functions*2 Functions*1*2
Retained*3 Functions Functions Retained*3
Retained
Retained
Retained
Halted
Halted
Retained*4
Event counter Reset Functions Functions Retained
PWM
Retained Retained Retained
Retained
Notes: 1. When an asynchronous external event is input, the counter increments but the counter
overflow H/L flags are not affected.
2. Functions when asynchronous external events are selected; halted and retained
otherwise.
3. Clock control by IRQAEC operates, but interrupts do not.
4. As the clock is stopped in module standby mode, IRQAEC has no effect.
9.4.6 Usage Notes
1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR in
8-bit mode and clear bit CUEL to 0 in 16-bit mode to prevent asynchronous event input to the
counter. The correct value will not be returned if the event counter increments while being
read.
2. The maximum clock frequency that may be input to the AEVH and AEVL pins is 16 MHz*1.
Furthermore, the clock high width and low width should be half or more the OSC clock cycle
time. The duty ratio does not matter as long as the high width and low width satisfy the
minimum requirement.
Rev. 7.00 Mar. 08, 2010 Page 250 of 510
REJ09B0024-0700