HD6473847RHV Datasheet, PDF (147/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 5 Power-Down Modes
5.1.2 System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit
7 to 5
Bit Name
⎯
Initial
Value
All 1
4
NESEL 1
3
DTON
0
2
MSON 0
1
SA1
0
0
SA0
0
Legend: X: Don't care.
R/W
⎯
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 1 and cannot be modi-
fied.
Noise Elimination Sampling Frequency Select
Selects the frequency at which the watch clock signal
(φ_W) generated by the subclock pulse generator is sam-
pled, in relation to the oscillator clock (φ_OSC) generated
by the system clock pulse generator. When φ_OSC = 2 to
16 MHz, clear this bit to 0.
0: Sampling rate is φ /16.
OSC
1: Sampling rate is φ_OSC/4.
Direct Transfer on Flag
Selects the mode to which the transition is made after
the SLEEP instruction is executed with bits SSBY and
LSON in SYSCR1, bit MSON in SYSCR2, and bit TMA3
in TMA.
For details, see table 5.2.
Medium Speed on Flag
After standby, watch, or sleep mode is cleared, this bit
selects active (high-speed) or active (medium-speed)
mode.
0: Operation in active (high-speed) mode
1: Operation in active (medium-speed) mode
Subactive Mode Clock Select 1 and 0
Select the operating clock frequency in subactive and
subsleep modes. The operating clock frequency
changes to the set frequency after the SLEEP instruc-
tion is executed.
00: φ_W/8
01: φ /4
W
1X: φ_W/2
Rev. 7.00 Mar. 08, 2010 Page 115 of 510
REJ09B0024-0700