HD6473847RHV Datasheet, PDF (154/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 5 Power-Down Modes
Function
Active Mode
Sleep Mode
High-
speed
Medium- High-
speed speed
Medium- Watch
speed Mode
Subac-
tive
Mode
Subsleep Stand-by
Mode Mode
Periph-
eral
modules
A/D con-
verter
LCD
Function- Function- Function- Function- Retained Retained Retained Retained
ing
ing
ing
ing
Function- Function- Function- Function- Function- Function- Function- Retained
ing
ing
ing
ing
ing/reta- ing/reta- ing/reta-
ined^*3
ined^*3
ined^*3
LVD
Function- Function- Function- Function- Function- Function- Function- Function-
ing
ing
ing
ing
ing
ing
ing
ing
Notes: 1. Register contents are retained. Output is the high-impedance state.
2. Functioning if φ_W/2 is selected as an internal clock, or halted and retained otherwise.
3. Functioning if φw, φw/2, or φw/4 is selected as a clock to be used. Halted and retained
otherwise.
4. Functioning if the timekeeping time-base function is selected.
5. An external interrupt request is ignored. Contents of the interrupt request register are
not affected.
6. The counter can be incremented. An interrupt cannot occur.
7. Functioning if φw/4 is selected as an internal clock. Halted and retained otherwise.
8. On the H8/38104 Group, operates when φw/32 is selected as the internal clock or the
on-chip oscillator is selected; otherwise stops and stands by. On the H8/38004,
H8/38002S Group, operates when φw/32 is selected as the internal clock; otherwise
stops and stands by.
9. On the H8/38104 Group, operates when φw/32 is selected as the internal clock or the
on-chip oscillator is selected; otherwise stops and stands by. On the H8/38004,
H8/38002S Group, stops and stands by.
10. On the H8/38104 Group, operates only when the on-chip oscillator is selected; other-
wise stops and stands by. On the H8/38004, H8/38002S Group, stops and stands by.
5.2.1 Sleep Mode
In sleep mode, CPU operation is halted but the system clock oscillator, subclock oscillator, and
on-chip peripheral modules function. In sleep (medium-speed) mode, the on-chip peripheral mod-
ules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1. CPU register con-
tents are retained.
Sleep mode is cleared by an interrupt. When an interrupt is requested, sleep mode is cleared and
interrupt exception handling starts. Sleep mode is not cleared if the I bit in CCR is set to 1 or the
requested interrupt is disabled by the interrupt enable bit. After sleep mode is cleared, a transition
is made from sleep (high-speed) mode to active (high-speed) mode or from sleep (medium-speed)
mode to active (medium-speed) mode.
Rev. 7.00 Mar. 08, 2010 Page 122 of 510
REJ09B0024-0700