HD6473847RHV Datasheet, PDF (279/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Start
Set CH2 to 1
Set ACKH1, ACKH0, ACKL1, ACKL0,
AHEGS1, AHEGS0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Section 9 Timers
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.9 Example of Software Processing when Using ECH and ECL as
8-Bit Event Counters
ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown
in the example in figure 9.9. When the next clock is input after the ECH count value reaches H'FF,
ECH overflows, the OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00, and
counting up is restarted. Similarly, when the next clock is input after the ECL count value reaches
H'FF, ECL overflows, the OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00,
and counting up is restarted. When an overflow occurs, the IRREC bit is set to 1 in IRR2. If the
IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU.
IRQAEC Operation: When ECPWME in AEGSR is 0, the ECH and ECL input clocks are
enabled only when IRQAEC is high. When IRQAEC is low, the input clocks are not input to the
counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be
controlled from outside by controlling IRQAEC. In this case, ECH and ECL cannot be controlled
individually.
IRQAEC can also operate as an interrupt source. In this case the vector number is 6 and the vector
addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge sensing can be selected for the IRQAEC input pin with bits AIAGS1
and AIAGS0 in AEGSR.
Rev. 7.00 Mar. 08, 2010 Page 247 of 510
REJ09B0024-0700