HD6473847RHV Datasheet, PDF (255/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 9 Timers
9.3.2 Input/Output Pins
Table 9.3 shows the pin configuration of the timer F.
Table 9.3 Pin Configuration
Name
Timer FH output
Timer FL output
Abbreviation I/O
TMOFH
Output
TMOFL
Output
Function
Timer FH toggle output pin
Timer FL toggle output pin
9.3.3 Register Descriptions
The timer F has the following registers.
• Timer counters FH and FL (TCFH,TCFL)
• Output compare registers FH and FL (OCRFH, OCRFL)
• Timer control register F (TCRF)
• Timer control status register F (TCSRF)
Timer Counters FH and FL (TCFH, TCFL): TCF is a 16-bit read/write up-counter configured
by cascaded connection of 8-bit timer counters TCFH and TCFL. In addition to the use of TCF as
a 16-bit counter with TCFH as the upper 8 bits and TCFL as the lower 8 bits, TCFH and TCFL
can also be used as independent 8-bit counters.
TCFH and TCFL can be read and written by the CPU, but when they are used in 16-bit mode, data
transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP,
see section 9.3.4, CPU Interface. TCFH and TCFL are initialized to H'00 upon reset.
• 16-bit mode (TCF)
When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input clock
is selected by bits CKSL2 to CKSL0 in TCRF.
TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an
interrupt request is sent to the CPU.
• 8-bit mode (TCFL/TCFH)
When CKSH2 is set to 1 in TCRF, TCFH and TCFL operate as two independent 8-bit
counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to
CKSL0) in TCRF.
Rev. 7.00 Mar. 08, 2010 Page 223 of 510
REJ09B0024-0700