HD6473847RHV Datasheet, PDF (303/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 10 Serial Communication Interface 3 (SCI3)
10.3.8 Bit Rate Register (BRR)
BRR is an 8-bit readable/writable register that adjusts the bit rate. BRR is initialized to H'FF at a
reset and in standby, watch, or module standby mode. Table 10.2 shows the relationship between
the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode.
Table 10.4 shows the maximum bit rate for each frequency in asynchronous mode. The values
shown in both tables 10.2 and 10.4 are values in active (high-speed) mode. Table 10.5 shows the
relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 in SMR in
clocked synchronous mode. The values are shown in table 10.5. The N setting in BRR and error
for other operating frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
N=
φ
32 × 2²ⁿ × B
–1
B (bit rate obtained from n, N, φ) – R (bit rate in left-hand column in table 10.2)
Error (%) =
R (bit rate in left-hand column in table 10.2)
× 100
Legend: B:
N:
φ:
n:
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (Hz)
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.3.)
Rev. 7.00 Mar. 08, 2010 Page 271 of 510
REJ09B0024-0700