HD6473847RHV Datasheet, PDF (301/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 10 Serial Communication Interface 3 (SCI3)
Initial
Bit
Bit Name Value R/W Description
5
OER
0
R/(W)^* Overrun Error
[Setting condition]
• When an overrun error occurs in reception
[Clearing condition]
• When 0 is written to OER after reading OER = 1
When bit RE in SCR3 is cleared to 0, bit OER is not
affected and retains its previous state.
When an overrun error occurs, RDR retains the receive
data it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be
continued with bit OER set to 1, and in clocked
synchronous mode, transmission cannot be continued
either.
4
FER
0
R/(W)^* Framing Error
[Setting condition]
• When a framing error occurs in reception
[Clearing condition]
• When 0 is written to FER after reading FER = 1
When bit RE in SCR3 is cleared to 0, bit FER is not
affected and retains its previous state.
Note that, in 2-stop-bit mode, only the first stop bit is
checked for a value of 1, and the second stop bit is not
checked. When a framing error occurs, the receive data
is transferred to RDR but bit RDRF is not set. Reception
cannot be continued with bit FER set to 1. In clocked
synchronous mode, neither transmission nor reception is
possible when bit FER is set to 1.
Rev. 7.00 Mar. 08, 2010 Page 269 of 510
REJ09B0024-0700