HD6473847RHV Datasheet, PDF (111/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 3 Exception Handling
3.2.3 Interrupt Enable Register 2 (IENR2)
IENR2 enables direct transition, A/D converter, and timer interrupts.
Initial
Bit
Bit Name Value R/W Description
7
IENDT 0
R/W Direct Transition Interrupt enable
Enables or disables direct transition interrupt requests.
0: Disables direct transition interrupt requests
1: Enables direct transition interrupt requests
6
IENAD 0
R/W A/D Converter Interrupt enable
Enables or disables A/D conversion end interrupt
requests.
0: Disables A/D converter interrupt requests
1: Enables A/D converter interrupt requests
5, 4 ⎯
⎯
W
Reserved
The write value should always be 0.
3
IENTFH 0
R/W Timer FH Interrupt Enable
Enables or disables timer FH compare match or overflow
interrupt requests.
0: Disables timer FH interrupt requests
1: Enables timer FH interrupt requests
2
IENTFL 0
R/W Timer FL Interrupt Enable
Enables or disables timer FL compare match or overflow
interrupt requests.
0: Disables timer FL interrupt requests
1: Enables timer FL interrupt requests
1
⎯
⎯
W
Reserved
The write value should always be 0.
0
IENEC 0
R/W Asynchronous Event Counter Interrupt Enable
Enables or disables asynchronous event counter interrupt
requests.
0: Disables asynchronous event counter interrupt
requests
1: Enables asynchronous event counter interrupt requests
For details on SCI3 interrupt control, refer to section 10.3.6, Serial Control Register 3 (SCR3).
Rev. 7.00 Mar. 08, 2010 Page 79 of 510
REJ09B0024-0700