HD6473847RHV Datasheet, PDF (84/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 2 CPU
Figure 2.10 shows the instruction formats of system control instructions.
15
87
0
op
RTE, SLEEP, NOP
15
87
op
0
rn
LDC, STC (Rn)
15
87
0
ANDC, ORC,
op
IMM
XORC, LDC (#xx:8)
Legend:
op: Operation field
rn: Register field
IMM: Immediate data
Figure 2.10 Instruction Formats of System Control Instructions
2.5.8 Block Data Transfer Instructions
Table 2.10 describes the block data transfer instructions.
Table 2.10 Block Data Transfer Instructions
Instruction Size
EEPMOV
—
Function
If R4L ≠ 0 then
repeat @R5+ → @R6+
R4L – 1 → R4L
until R4L = 0
else next;
Block data transfer instruction. Transfers the number of data bytes
specified by R4L from locations starting at the address indicated by R5
to locations starting at the address indicated by R6. After the transfer,
the next instruction is executed.
Certain precautions are required in using the EEPMOV instruction. See section 2.9.3, EEPMOV
Instruction, for details.
Rev. 7.00 Mar. 08, 2010 Page 52 of 510
REJ09B0024-0700