HD6473847RHV Datasheet, PDF (115/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 3 Exception Handling
3.2.7 Wakeup Edge Select Register (WEGR)
WEGR specifies rising or falling edge sensing for pins WKPn.
Initial
Bit
Bit Name Value R/W Description
7
WKEGS7 0
R/W WKPn Edge Select 7 to 0
6
WKEGS6 0
R/W Selects WKPn pin input sensing.
5
WKEGS5 0
R/W 0: WKPn pin falling edge is detected
4
WKEGS4 0
R/W 1: WKPn pin rising edge is detected
3
WKEGS3 0
R/W
(n = 7 to 0)
2
WKEGS2 0
R/W
1
WKEGS1 0
R/W
0
WKEGS0 0
R/W
3.3 Reset Exception Handling
When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of
the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure
that this LSI is reset at power-on, hold the RES pin low until the clock pulse generator output
stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock
cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts
reset exception handling. The reset exception handling sequence is shown in figure 3.1. The reset
exception handling sequence is as follows. However, refer to section 14.3.1, Power-On Reset
Circuit, for information on the reset sequence for the H8/38104 Group, which has a built-in
power-on reset function.
1. Set the I bit in the condition code register (CCR) to 1.
2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the
data in that address is sent to the program counter (PC) as the start address, and program
execution starts from that address.
Rev. 7.00 Mar. 08, 2010 Page 83 of 510
REJ09B0024-0700