HD6473847RHV Datasheet, PDF (489/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Appendix A Instruction Set
Table A.3 Number of States Required for Execution
Execution Status
(Instruction Cycle)
On-Chip Memory
Access Location
On-Chip Peripheral Module
Instruction fetch
S_I
2
—
Branch address read S_J
Stack operation
S
K
Byte data access
S
L
2 or 3^*
Word data access
S_M
—
Internal operation
S_N
1
Note: * Depends on which on-chip peripheral module is accessed. See section 16.1, Register
Addresses (Address Order).
Table A.4 Number of Cycles in Each Instruction
Instruction Mnemonic
ADD
ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W Rs, Rd
ADDS
ADDS.W #1, Rd
ADDS.W #2, Rd
ADDX
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
AND
AND.B #xx:8, Rd
AND.B Rs, Rd
ANDC
ANDC #xx:8, CCR
BAND
BAND #xx:3, Rd
BAND #xx:3, @Rd
BAND #xx:3, @aa:8
Instruction Branch Stack Byte Data Word Data Internal
Fetch
Addr. Read Operation Access Access Operation
I
J
K
L
M
N
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
Rev. 7.00 Mar. 08, 2010 Page 457 of 510
REJ09B0024-0700