HD6473847RHV Datasheet, PDF (335/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 10 Serial Communication Interface 3 (SCI3)
should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is
sufficient margin in an RDR read operation before reception of the next frame is completed. To be
precise in terms of timing, the RDR read should be completed before bit 7 is transferred in clocked
synchronous mode, or before the STOP bit is transferred in asynchronous mode.
10.7.8 Transmit and Receive Operations when Making State Transition
Make sure that transmit and receive operations have completely finished before carrying out state
transition processing.
10.7.9 Setting in Subactive or Subsleep Mode
In subactive or subsleep mode, the SCI3 can operate only when the CPU clock is φ_W/2. The SA1
bit in SYSCR2 should be set to 1.
10.7.10 Oscillator Use with Serial Communication Interface 3 in Asynchronous Mode
(H8/38104 Group Only)
When implementing serial communication interface 3 in asynchronous mode on the H8/38104
Group, the system clock oscillator must be used. The on-chip oscillator should not be used in this
case. See section 4.3.4, On-Chip Oscillator Selection Method, for information on switching
between the system clock oscillator and the on-chip oscillator.
Rev. 7.00 Mar. 08, 2010 Page 303 of 510
REJ09B0024-0700