HD6473847RHV Datasheet, PDF (331/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 10 Serial Communication Interface 3 (SCI3)
TDR (next transmit data)
TDR
TXD32 pin
TSR (transmission in progress)
TXD32 pin
↓
TSR (transmission completed, transfer)
TDRE = 0
TDRE 1
(TXI request when TIE = 1)
Figure 10.15(b) TDRE Setting and TXI Interrupt
TDR
TDR
TXD32 pin
TSR (transmission in progress)
TXD32 pin
TSR (transmission completed)
TEND = 0
TEND 1
(TEI request when TEIE = 1)
Figure 10.15(c) TEND Setting and TEI Interrupt
10.7 Usage Notes
10.7.1 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RXD32 pin
value directly. In a break, the input from the RXD32 pin becomes all 0, setting the FER flag, and
possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a
break, even if the FER flag is cleared to 0, it will be set to 1 again.
10.7.2 Mark State and Break Sending
When TE is 0, the TXD32 pin is used as an I/O port whose direction (input or output) and level
are determined by PCR and PDR. This can be used to set the TXD32 pin to mark state (high level)
or send a break during serial data transmission. To maintain the communication line at mark state
until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TXD32 pin
becomes an I/O port, and 1 is output from the TXD32 pin. To send a break during serial
transmission, first set PCR to 1 and PDR to 0, and then clear TE to 0. When TE is cleared to 0, the
Rev. 7.00 Mar. 08, 2010 Page 299 of 510
REJ09B0024-0700