HD6473847RHV Datasheet, PDF (105/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 3 Exception Handling
Section 3 Exception Handling
Exception handling may be caused by a reset or interrupts.
• Reset
A reset has the highest exception priority. Exception handling starts as soon as the reset is
cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and
exception handling starts. Exception handling is the same as exception handling by the RES
pin.
• Interrupts
External interrupts and internal interrupts are masked by the I bit in CCR, and kept masked
while the I bit is set to 1. Exception handling starts when the current instruction or exception
handling ends, if an interrupt request has been issued.
The following notes apply to the HD64F38004.
• Issue
Depending on the circuitry status at power-on, a vector 17 (system reservation) interrupt
request may be generated. If bit I in CCR is cleared to 0, this interrupt will be accepted just
like any other internal interrupt. This can cause processing exceptions to occur, and program
execution will eventually halt since there is no procedure for clearing the interrupt request flag
in question.
• Countermeasure
To prevent the above issue from occurring, it is recommended that the following steps be
added to programs written for the product.
Rev. 7.00 Mar. 08, 2010 Page 73 of 510
REJ09B0024-0700