HD6473847RHV Datasheet, PDF (281/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 9 Timers
Table 9.6 Examples of Event Counter PWM Operation
Conditions: fosc = 4 MHz, fφ = 2 MHz, high-speed active mode, ECPWCR value (Ncm) =
H'7A11, ECPWDR value (Ndr) = H'16E3
Clock
Clock
Source Source ECPWMCR ECPWMDR
Selection Cycle (T)^* Value (Ncm) Value (Ndr)
φ/2
1 µs
H'7A11
H'16E3
φ/4
2 µs
D'31249
D'5859
φ/8
4 µs
φ/16
8 µs
φ/32
16 µs
φ/64
32 µs
Note: * toff minimum width
toff = T ×
(Ndr + 1)
5.86 ms
11.72 ms
23.44 ms
46.88 ms
93.76 ms
187.52 ms
tcm = T ×
(Ncm + 1)
31.25 ms
62.5 ms
125.0 ms
250.0 ms
500.0 ms
1000.0 ms
ton = tcm –
toff
25.39 ms
50.78 ms
101.56 ms
203.12 ms
406.24 ms
812.48 ms
Clock Input Enable/Disable Function Operation: The clock input to the event counter can be
controlled by the IRQAEC pin when ECPWME in AEGSR is 0, and by the event counter PWM
output, IECPWM when ECPWME in AEGSR is 1. As this function forcibly terminates the clock
input by each signal, a maximum error of one count will occur depending on the IRQAEC or
IECPWM timing.
Figure 9.11 shows an example of the operation of this function.
Input event
IRQAEC or IECPWM
Actually counted clock source
Edge generated by clock return
Counter value _N
N+1
N+2
N+3
N+4
Clock stopped
Figure 9.11 Example of Clock Control Operation
N+5
N+6
Rev. 7.00 Mar. 08, 2010 Page 249 of 510
REJ09B0024-0700