HD6473847RHV Datasheet, PDF (275/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 9 Timers
Event Counter Control/Status Register (ECCSR): ECCSR controls counter overflow detection,
counter clear resetting, and the count-up function.
Initial
Bit
Bit Name Value R/W Description
7
OVH
0
R/W^* Counter Overflow H
This is a status flag indicating that ECH has overflowed.
[Setting condition]
When ECH overflows from H’FF to H’00
[Clearing condition]
6
OVL
0
When this bit is written to 0 after reading OVH = 1
R/W^* Counter Overflow L
This is a status flag indicating that ECL has overflowed.
[Setting condition]
When ECL overflows from H'FF to H'00
[Clearing condition]
When this bit is written to 0 after reading OVL = 1
5
⎯
0
R/W Reserved
This bit can be read from or written to. However, the initial
value should not be changed.
4
CH2
0
R/W Channel Select
Selects how ECH and ECL event counters are used
0: ECH and ECL are used together as a single-channel
16-bit event counter
1: ECH and ECL are used as two-channel 8-bit event
counter
3
CUEH
0
R/W Count-Up Enable H
Enables event clock input to ECH.
0: ECH event clock input is disabled (ECH value is
retained)
1: ECH event clock input is enabled
2
CUEL
0
R/W Count-Up Enable L
Enables event clock input to ECL.
0: ECL event clock input is disabled (ECL value is
retained)
1: ECL event clock input is enabled
Rev. 7.00 Mar. 08, 2010 Page 243 of 510
REJ09B0024-0700