HD6473847RHV Datasheet, PDF(317/546 Page) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

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HD6473847RHV Datasheet, PDF (317/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

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Section 10 Serial Communication Interface 3 (SCI3)

10.4.4 Serial Data Reception

Figure 10.7 shows an example of operation for reception in asynchronous mode. In serial

reception, the SCI operates as described below.

1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs

internal synchronization, receives data in RSR, and checks the parity bit and stop bit.

â¢ Parity check

The SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or

even) set in bit PM in the serial mode register (SMR).

â¢ Stop bit check

The SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.

â¢ Status check

The SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred

from RSR to RDR.

2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag

is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time,

an ERI interrupt request is generated. Receive data is not transferred to RDR.

3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to

RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated.

4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and

receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI

interrupt request is generated.

5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is

transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is

generated. Continuous reception is possible because the RXI interrupt routine reads the

receive data transferred to RDR before reception of the next receive data has been completed.

Rev. 7.00 Mar. 08, 2010 Page 285 of 510

REJ09B0024-0700

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