HD6473847RHV Datasheet, PDF (113/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 3 Exception Handling
3.2.5 Interrupt Request Register 2 (IRR2)
IRR2 is a status flag register for direct transition, A/D converter, timer FH, timer FL, and
asynchronous event counter interrupt requests. The corresponding flag is set to 1 when an interrupt
request occurs. The flags are not cleared automatically when an interrupt is accepted. It is
necessary to write 0 to clear each flag.
Initial
Bit
Bit Name Value R/W Description
7
IRRDT 0
R/W^* Direct Transition Interrupt Request Flag
[Setting condition]
When a direct transition is made by executing a SLEEP
instruction while the DTON bit = 1
[Clearing condition]
When IRRDT = 1, it is cleared by writing 0
6
IRRAD 0
R/W^* A/D Converter Interrupt Request Flag
[Setting condition]
When A/D conversion is completed and the ADSF bit is
cleared to 0
[Clearing condition]
When IRRAD = 1, it is cleared by writing 0
5, 4 ⎯
⎯
W
Reserved
The write value should always be 0.
3
IRRTFH 0
R/W^* Timer FH Interrupt Request Flag
[Setting condition]
When TCFH and OCRFH match in 8-bit timer mode, or
when TCF (TCFL, TCFH) and OCRF (OCRFL, OCRFH)
match in 16-bit timer mode
[Clearing condition]
When IRRTFH = 1, it is cleared by writing 0
2
IRRTFL 0
R/W^* Timer FL Interrupt Request Flag
[Setting condition]
When TCFL and OCRFL match in 8-bit timer mode
[Clearing condition]
When IRRTFL = 1, it is cleared by writing 0
1
⎯
⎯
W
Reserved
The write value should always be 0.
Rev. 7.00 Mar. 08, 2010 Page 81 of 510
REJ09B0024-0700