HD6473847RHV Datasheet, PDF (297/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 10 Serial Communication Interface 3 (SCI3)
Initial
Bit
Bit Name Value R/W Description
1
CKS1
0
R/W Clock Select 0 and 1
0
CKS0
0
R/W These bits select the clock source for the on-chip baud
rate generator.
00: φ clock (n = 0)
01: φw/2 or φw clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
When the setting value is 01 in active mode and sleep
mode, φw/2 clock is set. In subactive mode and subsleep
mode, φw clock is set. The SCI3 is enabled only when φw
/2 is selected for the CPU operating clock.
For the relationship between the bit rate register setting
and the baud rate, see section 10.3.8, Bit Rate Register
(BRR). n is the decimal representation of the value of n in
BRR (see section 10.3.8, Bit Rate Register (BRR)).
Rev. 7.00 Mar. 08, 2010 Page 265 of 510
REJ09B0024-0700