HD6473847RHV Datasheet, PDF (116/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 3 Exception Handling
3.4 Interrupt Exception Handling
3.4.1 External Interrupts
There are external interrupts, WKP7 to WKP0, IRQ1, IRQ0, and IRQAEC.
WKP7 to WKP0 Interrupts
WKP7 to WKP0 interrupts are requested by input signals to pins WKP7 to WKP0. These
interrupts have the same vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of bits WKEGS7 to WKEGS0 in
WEGR.
When pins WKP7 to WKP0 are designated for interrupt input in PMR5 and the designated signal
edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These
interrupts can be masked by setting bit IENWP in IENR1.
IRQ1 and IRQ0 Interrupts
IRQ1 and IRQ0 interrupts are requested by input signals to pins IRQ1 and IRQ0. These interrupts
are given different vector addresses, and are detected individually by either rising edge sensing or
falling edge sensing, depending on the settings of bits IEG1 and IEG0 in IEGR.
When pins IRQ1 and IRQ0 are designated for interrupt input by PMRB and PMR2 and the
designated signal edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an
interrupt. These interrupts can be masked by setting bits IEN1 and IEN0 in IENR1.
Rev. 7.00 Mar. 08, 2010 Page 84 of 510
REJ09B0024-0700