HD6473847RHV Datasheet, PDF (284/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 9 Timers
9.5 Watchdog Timer
The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
However, as shown in watchdog timer block diagrams figure 9.12 (1) and figure 9.12 (2), the
implementation differs in the H8/38004, H8/38002S Group and the H8/38104 Group.
9.5.1 Features
• Selectable from two counter input clocks (H8/38004, H8/38002S Group).
Two clock sources (φ/8192 or φ_W/32) can be selected as the timer-counter clock.
• On the H8/38104 Group, 10 internal clocks are available for selection. Ten internal clocks
(φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φw/32, or watchdog on-chip
oscillator) can be selected as the timer-counter clock.
• Reset signal generated on counter overflow
An overflow period of 1 to 256 times the selected clock can be set.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 5.4, Module Standby Function.)
φw/32
φ
PSS
φ/8192
TCSRW
TCW
Legend:
TCSRW: Timer control/status register W
TCW: Timer counter W
PSS: Prescaler S
Internal reset
signal
Figure 9.12(1) Block Diagram of Watchdog Timer (H8/38004, H8/38002S Group)
Rev. 7.00 Mar. 08, 2010 Page 252 of 510
REJ09B0024-0700