HD6473847RHV Datasheet, PDF (259/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 9 Timers
Bit
3
2
1
0
Note:
Initial
Bit Name Value R/W Description
OVFL
0
R/W^* Timer Overflow Flag L
This is a status flag indicating that TCFL has overflowed.
[Setting condition]
When TCFL overflows from H’FF to H’00
[Clearing condition]
When this bit is written to 0 after reading OVFL = 1
CMFL
0
R/W^* Compare Match Flag L
This is a status flag indicating that TCFL has matched
OCRFL.
[Setting condition]
When the TCFL value matches the OCRFL value
[Clearing condition]
When this bit is written to 0 after reading CMFL = 1
OVIEL 0
R/W Timer Overflow Interrupt Enable L
Selects enabling or disabling of interrupt generation when
TCFL overflows.
0: TCFL overflow interrupt request is disabled
1: TCFL overflow interrupt request is enabled
CCLRL 0
R/W Counter Clear L
Selects whether TCFL is cleared when TCFL and OCRFL
match.
0: TCFL clearing by compare match is disabled
1: TCFL clearing by compare match is enabled
* Only 0 can be written to clear the flag.
9.3.4 CPU Interface
TCF and OCRF are 16-bit readable/writable registers, but the CPU is connected to the on-chip
peripheral modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses
an 8-bit temporary register (TEMP).
When performing TCF read/write access or OCRF write access in 16-bit mode, data will not be
transferred correctly if only the upper byte or only the lower byte is accessed. Access must be
performed for all 16 bits (using two consecutive byte-size MOV instructions), and the upper byte
must be accessed before the lower byte.
Rev. 7.00 Mar. 08, 2010 Page 227 of 510
REJ09B0024-0700