HD6473847RHV Datasheet, PDF (163/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 5 Power-Down Modes
2. When external input signals cannot be captured because internal clock stops
The case of falling edge capture is shown in figure 5.3.
As shown in the case marked "Capture not possible," when an external input signal falls im-
mediately after a transition to active (high-speed or medium-speed) mode or subactive mode,
after oscillation is started by an interrupt via a different signal, the external input signal cannot
be captured if the high-level width at that point is less than 2 tcyc or 2 . tsubcyc
3. Recommended timing of external input signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of
at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch
mode, as shown in "Capture possible: case 1."
External input signal capture is also possible with the timing shown in "Capture possible: case
2" and "Capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured.
Active (high-speed, medium-speed)
Operating mode mode or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
Standby mode or
watch mode
Wait for osc-
illation
stabilization
Active (high-speed, medium-speed)
mode or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
φ or φSUB
External input signal
Capture possible: case 1
Capture possible: case 2
Capture possible: case 3
Capture not possible
Interrupt by different signal
Figure 5.3 External Input Signal Capture when Signal Changes before/after Standby Mode
or Watch Mode
4. Input pins to which these notes apply:
IRQ1, IRQ0, WKP7 to WKP0, and IRQAEC
Rev. 7.00 Mar. 08, 2010 Page 131 of 510
REJ09B0024-0700