HD6473847RHV Datasheet, PDF (122/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 3 Exception Handling
In the above example, an IRQ0 interrupt occurs while the AND.B instruction is executed. Since
not only the original target IRRI1, but also IRRI0 is cleared to 0, the IRQ0 interrupt becomes
invalid.
3.5.4 Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, IRQAEC,
IRQ1, IRQ0, and WKP7 to WKP0, the interrupt request flag may be set to 1.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0.
Table 3.3 lists the interrupt request flags which are set to 1 and the conditions.
Table 3.3 Conditions under which Interrupt Request Flag Is Set to 1
Interrupt Request Flags
Set to 1
Conditions
IRR1
IRREC2
When the edge designated by AIEGS1 and AIEGS0 in AEGSR is input
while IENEC2 in IENRI is set to 1.
IRRI1
When IRQ1 bit in PMRB is changed from 0 to 1 while pin IRQ1 is low
and IEG1 bit in IEGR = 0.
When IRQ1 bit in PMRB is changed from 1 to 0 while pin IRQ1 is low
and IEG1 bit in IEGR = 1.
IRRI0
When IRQ0 bit in PMR2 is changed from 0 to 1 while pin IRQ0 is low
and IEG0 bit in IEGR = 0.
When IRQ0 bit in PMR2 is changed from 1 to 0 while pin IRQ0 is low
and IEG0 bit in IEGR = 1.
Rev. 7.00 Mar. 08, 2010 Page 90 of 510
REJ09B0024-0700