HD6473847RHV Datasheet, PDF (280/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 9 Timers
Note: On the H8/38104 Group, control of switching between the system clock oscillator and the
on-chip oscillator during resets should be performed by setting the IRQAEC input level.
Refer to section 4.4, Subclock Generator, for details.
Event Counter PWM Operation: When ECPWME in AEGSR is 1, the ECH and ECL input
clocks are enabled only when event counter PWM output (IECPWM) is high. When IECPWM is
low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and
ECL count operations can therefore be controlled cyclically from outside by controlling event
counter PWM. In this case, ECH and ECL cannot be controlled individually.
IECPWM can also operate as an interrupt source. In this case the vector number is 6 and the
vector addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits
AIAGS1 and AIAGS0 in AEGSR.
Figure 9.10 and table 9.6 show examples of event counter PWM operation.
toff = T • (Ndr +1)
ton
tcm = T • (Ncm +1)
Legend:
ton: Clock input enable time
toff: Clock input disable time
tcm: One conversion period
T: ECPWM input clock cycle
Ndr: Value of ECPWDRH and ECPWDRL
Fixed low when Ndr = H'FFFF
Ncm: Value of ECPWCRH and ECPWCRL
Figure 9.10 Event Counter Operation Waveform
Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this
condition, do not set ECPWME to 1 in AEGSR.
Rev. 7.00 Mar. 08, 2010 Page 248 of 510
REJ09B0024-0700