HD6473847RHV Datasheet, PDF(309/546 Page) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

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HD6473847RHV Datasheet, PDF (309/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

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Section 10 Serial Communication Interface 3 (SCI3)

Initial

Bit

Bit Name Value R/W Description

2

SCINV2 0

R/W RXD32 Pin Input Data Inversion Switch

This bit selects whether or not the logic level of the

RXD32 pin input data is inverted.

0: RXD32 input data is not inverted

1: RXD32 input data is inverted

1, 0 â¯

â¯

W

Reserved

The write value should always be 0.

Note:

When the serial port control register is modified, the data being input or output up to that

point is inverted immediately after the modification, and an invalid data change is input or

output. When modifying the serial port control register, modification must be made in a state

in which data changes are invalidated.

10.4 Operation in Asynchronous Mode

Figure 10.2 shows the general format for asynchronous serial communication. One frame consists

of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and

finally stop bits (high level). In asynchronous mode, synchronization is performed at the falling

edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a

frequency 16 times the bit period, so that the transfer data is latched at the center of each bit.

Inside the SCI3, the transmitter and receiver are independent units, enabling full duplex. Both the

transmitter and the receiver also have a double-buffered structure, so data can be read or written

during transmission or reception, enabling continuous data transfer. Table 10.7 shows the 16 data

transfer formats that can be set in asynchronous mode. The format is selected by the settings in

SMR as shown in table 10.8.

LSB

Serial Start

data bit

Transmit/receive data

MSB

Parity

bit

Stop bit

1

Mark state

1 bit

5, 7, or 8 bits

1 bit,

1 or

or none 2 bits

One unit of transfer data (character or frame)

Figure 10.2 Data Format in Asynchronous Communication

Rev. 7.00 Mar. 08, 2010 Page 277 of 510

REJ09B0024-0700

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