HD6473847RHV Datasheet, PDF (135/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

4.5 Prescalers
Section 4 Clock Pulse Generators
4.5.1 Prescaler S
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once
per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from
the reset state. In standby mode, watch mode, subactive mode, and subsleep mode, the system
clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot
read or write prescaler S. The output from prescaler S is shared by the on-chip peripheral modules.
The division ratio can be set separately for each on-chip peripheral function. In active (medium-
speed) mode and sleep mode, the clock input to prescaler S is determined by the division ratio
designated by the MA1 and MA0 bits in SYSCR2.
4.5.2 Prescaler W
Prescaler W is a 5-bit counter using a 32.768 kHz or 38.4 kHz signal divided by 4 (φ_W/4) as its
input clock. The divided output is used for clock time base operation of timer A. Prescaler W is
initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby
mode, watch mode, subactive mode, or subsleep mode, prescaler W continues functioning.
Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 in TMA.
4.6 Usage Notes
4.6.1 Note on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Resonator circuit constants will differ
depending on the resonator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the resonator manufacturer.
Design the circuit so that the resonator never receives voltages exceeding its maximum rating.
Rev. 7.00 Mar. 08, 2010 Page 103 of 510
REJ09B0024-0700