HD6473847RHV Datasheet, PDF (157/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 5 Power-Down Modes
The operating frequency of subactive mode is selected from φ_W/2, φ_W/4, and φ_W/8 by the SA1 and
SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to
the frequency which is set before the execution.
5.2.6 Active (Medium-Speed) Mode
In active (medium-speed) mode, the system clock oscillator, subclock oscillator, CPU, and on-
chip peripheral modules function.
Active (medium-speed) mode is cleared by the SLEEP instruction. When active (medium-speed)
mode is cleared, a transition to standby mode is made depending on the combination of bits SSBY
and LSON in SYSCR1 and bit TMA3 in TMA, a transition to watch mode is made depending on
the combination of bit SSBY in SYSCR1 and bit TMA3 in TMA, or a transition to sleep mode is
made depending on the combination of bits SSBY and LSON in SYSCR1. Moreover, a transition
to active (high-speed) mode or subactive mode is made by a direct transition. Active (medium-
sleep) mode is not entered if the I bit in CCR is set to 1 or the requested interrupt is disabled in the
interrupt enable register. When the RES pin goes low, the CPU goes into the reset state and active
(medium-sleep) mode is cleared.
Furthermore, it sometimes operates with half state early timing at the time of transition to active
(medium-speed) mode.
In active (medium-speed) mode, the on-chip peripheral modules function at the clock frequency
set by the MA1 and MA0 bits in SYSCR1.
Rev. 7.00 Mar. 08, 2010 Page 125 of 510
REJ09B0024-0700