HD6473847RHV Datasheet, PDF (156/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 5 Power-Down Modes
exception handling starts. Watch mode is not cleared if the I bit in CCR is set to 1 or the requested
interrupt is disabled by the interrupt enable bit.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
5.2.4 Subsleep Mode
In subsleep mode, the CPU operation stops but on-chip peripheral modules other than the A/D
converter and PWM function. As long as a required voltage is applied, the contents of CPU regis-
ters, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O
ports keep the same states as before the transition.
Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared
and interrupt exception handling starts. After subsleep mode is cleared, a transition is made to
subactive mode. Subsleep mode is not cleared if the I bit in CCR is set to 1 or the requested inter-
rupt is disabled in the interrupt enable register.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
5.2.5 Subactive Mode
In subactive mode, the system clock oscillator stops but on-chip peripheral modules other than the
A/D converter and PWM function. As long as a required voltage is applied, the contents of some
registers of the on-chip peripheral modules are retained.
Subactive mode is cleared by the SLEEP instruction. When subacitve mode is cleared, a transition
to subsleep mode, active mode, or watch mode is made, depending on the combination of bits
SSBY and LSON in SYSCR1, bits MSON and DTON in SYSCR2, and bit TMA3 in TMA.
Subactive mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled in
the interrupt enable register.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
Rev. 7.00 Mar. 08, 2010 Page 124 of 510
REJ09B0024-0700