HD6473847RHV Datasheet, PDF (374/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 13 LCD Controller/Driver
Table 13.5 Output Levels
Data
M
Static
Common output
Segment output
1/2 duty Common output
Segment output
1/3 duty Common output
Segment output
1/4 duty Common output
Segment output
M: LCD alternation signal
0
0
V1
V1
V2, V3
V1
V3
V2
V3
V2
0
1
VSS
VSS
V2, V3
VSS
V2
V3
V2
V3
1
0
V1
VSS
V1
VSS
V1
VSS
V1
VSS
1
1
VSS
V1
VSS
V1
VSS
V1
VSS
V1
13.4.3 Operation in Power-Down Modes
In this LSI, the LCD controller/driver can be operated even in the power-down modes. The
operating state of the LCD controller/driver in the power-down modes is summarized in table
13.6.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless φ_W, φ_W/2, or φ_W/4 has been selected by bits CKS3 to CKS0, the clock will not be
supplied and display will halt. Since there is a possibility that a direct current will be applied to the
LCD panel in this case, it is essential to ensure that φ_W, φ_W/2, or φ_W/4 is selected.
In active (medium-speed) mode, the system clock is switched, and therefore bits CKS3 to CKS0
must be modified to ensure that the frame frequency does not change.
Rev. 7.00 Mar. 08, 2010 Page 342 of 510
REJ09B0024-0700