HD6473847RHV Datasheet, PDF (126/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 4 Clock Pulse Generators
IRQAEC
OSC1
OSC2
X1
X2
Internal reset signal (other than watchdog timer or low-voltage detect
circuit reset)
C
D
Q
Latch
System
clock
oscillator
φOSC
(fOSC)
System
clock
divider
(1/2)
On-chip _ROSC
oscillator
φOSC/2
System
clock
divider
φOSC/16
φOSC/32
φOSC/64
φOSC/128
System clock pulse generator
Subclock
φW
oscillator
(fW)
Subclock
divider
(1/2, 1/4, 1/8)
φW/2
φW/4
φW/8
Subclock pulse generator
φ
Prescaler S
(13 bits)
φ/2
to
φ/8192
φW
φSUB
Prescaler W
(5 bits)
φW/2
φW/4
φW/8
to
φW/128
Figure 4.2 Block Diagram of Clock Pulse Generators (H8/38104 Group)
The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φ_SUB. The
system clock is divided by prescaler S to become a clock signal from φ/8192 to φ/2, and the
subclock is divided by prescaler W to become a clock signal from φw/128 to φw/8. Both the
system clock and subclock signals are provided to the on-chip peripheral modules.
Rev. 7.00 Mar. 08, 2010 Page 94 of 510
REJ09B0024-0700