EP2S90F1020C5 Datasheet, PDF (766/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Summary
route the DCLK trace (see the “Signal Trace Routing”section). If your
design uses more than five configuration devices, Altera recommends
using buffers to split the fan-out on the DCLK signal.
f
JTAG
As PCBs become more complex, testing becomes increasingly important.
Advances in surface mount packaging and PCB manufacturing have
resulted in smaller boards, making traditional test methods such as
external test probes and “bed-of-nails” test fixtures harder to implement.
As a result, cost savings from PCB space reductions can be offset by cost
increases in traditional testing methods.
In addition to boundary scan testing (BST), you can use the IEEE
Std. 1149.1 controller for in-system programming. JTAG consists of four
required pins, test data input (TDI), test data output (TDO), test mode
select (TMS), and test clock input (TCK) as well as an optional test reset
input (TRST) pin.
Use the same guidelines for laying out clock signals to route TCK traces.
Use multiple devices for long JTAG scan chains. Minimize the JTAG scan
chain trace length that connects one device’s TDO pins to another device’s
TDI pins to reduce delay.
See Application Note 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in
Altera Devices for additional details on BST.
Test Point
As device package pin density increases, it becomes more difficult to
attach an oscilloscope or a logic analyzer probe on the device pin. Using
a physical probe directly on to the device pin can damage the device. If
the ball grid array (BGA) or FineLine BGA^® package is mounted on top
of the board, it is difficult to probe the other side of the board. Therefore,
the PCB must have a permanent test point to probe. The test point can be
a via that connects to the signal under test with a very short stub.
However, placing a via on a trace for a signal under test can cause
reflection and poor signal integrity.
Summary
You must carefully plan out a successful high-speed PCB. Factors such as
noise generation, signal reflection, crosstalk, and ground bounce can
interfere with a signal, especially with the high speeds that Altera devices
transmit and receive. The signal routing, termination schemes, and power
distribution techniques discussed in this chapter contribute to a more
effectively designed PCB using high-speed Altera devices.
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Stratix II Device Handbook, Volume 2
Altera Corporation
May 2007