EP2S90F1020C5 Datasheet, PDF (374/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Memory Modes
Table 2–11. Stratix II and Stratix II GX M-RAM Block Mixed-Width
Configurations (Simple Dual-Port Mode)
Read Port
64K × 9
32K × 18
18K × 36
8K × 72
4K × 144
Write Port
64K × 9 32K × 18 18K × 36 8K × 72
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
4K × 144
v
In simple dual-port mode, M512 and M4K blocks have one write enable
and one read enable signal. However, M-RAM blocks contain only a
write-enable signal, which is held high to perform a write operation.
M-RAM blocks are always enabled for read operations. If the read
address and the write address select the same address location during a
write operation, M-RAM block output is unknown.
TriMatrix memory blocks do not support a clear port on the write enable
and read enable registers. When the read enable is deactivated, the
current data is retained at the output ports. If the read enable is activated
during a write operation with the same address location selected, the
simple dual-port RAM output is either unknown or can be set to output
the old data stored at the memory address. Refer to “Read-During-Write
Operation at the Same Address” on page 2–33 for more information.
Figure 2–8 shows timing waveforms for read and write operations in
simple dual-port mode.
2–14
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008