EP2S90F1020C5 Datasheet, PDF (368/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

TriMatrix Memory Overview
Address Clock Enable Support
Stratix II and Stratix II GX M4K and M-RAM memory blocks support
address clock enable, which is used to hold the previous address value for
as long as the signal is enabled. When the memory blocks are configured
in dual-port mode, each port has its own independent address clock
enable.
Figure 2–2 shows an address clock enable block diagram. Placed in the
address register, the address signal output by the address register is fed
back to the input of the register via a multiplexer. The multiplexer output
is selected by the address clock enable (addressstall) signal. Address
latching is enabled when the addressstall signal turns high. The
output of the address register is then continuously fed into the input of
the register; therefore, the address value can be held until the
addressstall signal turns low.
Figure 2–2. Stratix II and Stratix II GX Address Clock Enable Block Diagram
address[0]
1
address[0]
0
register
address[0]
address[N]
addressstall
clock
1
address[N]
0
register
address[N]
Address clock enable is typically used for cache memory applications,
which require one port for read and another port for write. The default
value for the address clock enable signals is low (disabled). Figures 2–3
and 2–4 show the address clock enable waveform during the read and
write cycles, respectively.
2–8
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008