EP2S90F1020C5 Datasheet, PDF (539/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

DSP Blocks in Stratix II and Stratix II GX Devices
Figure 6–8. Simple Multiplier Mode
mult_round (1)
mult_saturate (1)
signa (1)
signb (1)
shiftinb
shiftina
sourcea
aclr[3..0]
clock[3..0]
ena[3..0]
Data A
sourceb
Data B
DQ
ENA
CLRN
DQ
ENA
CLRN
Q1.15
Round/
Saturate
(3)
DQ
ENA
Output Register
Data Out
CLRN
DQ
ENA
CLRN
Multiplier Block
DQ
ENA
CLRN
mult_is_saturated (2)
DSP Block
shiftoutb shiftouta
Notes to Figure 6–8:
(1) These signals are not registered or registered once to match the data path pipeline.
(2) This signal has the same latency as the data path.
(3) The rounding and saturation is only supported in 18- × 18-bit signed multiplication for Q1.15 inputs.
The multiplier operands can accept signed integers, unsigned integers or
a combination of both. The signa and signb signals can be changed
dynamically and can be registered in the DSP block. Additionally, the
multiplier inputs and result can be registered independently. The pipeline
registers within the DSP block can be used to pipeline the multiplier
result, increasing the performance of the DSP block.
36-Bit Multiplier
The 36-bit multiplier is also a simple multiplier mode but uses the entire
DSP block, including the adder/output block to implement the
36 × 36-bit multiplication operation. The device inputs 18-bit sections of
the 36-bit input into the four 18-bit multipliers. The adder/output block
adds the partial products obtained from the multipliers using the
summation block. Pipeline registers can be used between the multiplier
stage and the summation block to speed up the multiplication. The
36 × 36-bit multiplier supports signed, unsigned as well as mixed sign
multiplication. Figure 6–9 shows the DSP block configured to implement
a 36-bit multiplier.
Altera Corporation
January 2008
6–23
Stratix II Device Handbook, Volume 2