EP2S90F1020C5 Datasheet, PDF (410/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Stratix II and Stratix II GX DDR Memory Support Overview
voltage, and temperature (PVT) variations. This phase-shift circuitry has
been enhanced in Stratix II and Stratix II GX devices to support more
phase-shift options with less jitter.
Besides the DQS dedicated phase-shift circuitry, each DQS and DQSn pin
has its own DQS logic block that sets the delay for the signal input to the
pin. Using the DQS dedicated phase-shift circuitry with the DQS logic
block allows for phase-shift fine-tuning. Additionally, every IOE in a
Stratix II or Stratix II GX device contains six registers and one latch to
achieve DDR operation.
DDR Memory Interface Pins
Stratix II and Stratix II GX devices use data (DQ), data strobe (DQS and
DQSn), and clock pins to interface with external memory.
Figure 3–6 shows the DQ, DQS, and DQSn pins in the Stratix II or
Stratix II GX I/O banks on the top of the device. A similar arrangement is
repeated at the bottom of the device.
Figure 3–6. DQ and DQS Pins Per I/O Bank
Up to 8 Sets of
DQ & DQS Pins
DQ
Pins
Up to 10 Sets of
DQ & DQS Pins
DQ
Pins
I/O
Bank 3
DQSn
DQS
Pin
Pin
PLL 11
I/O
Bank 11
PLL 5
I/O
Bank 9
DQS
Phase
Shift
Circuitry
I/O
Bank 4
DQSn
DQS
Pin
Pin
Data and Data Strobe Pins
Stratix II and Stratix II GX data pins for the DDR memory interfaces are
called DQ pins. Stratix II and Stratix II GX devices can use either
bidirectional data strobes or unidirectional read clocks. Depending on the
external memory interface, either the memory device’s read data strobes
or read clocks feed the Stratix II or Stratix II GX DQS (and DQSn) pins.
3–14
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008