EP2S90F1020C5 Datasheet, PDF (699/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II and Stratix II GX Devices
Table 9–2. Stratix II and Stratix II GX Device Boundary Scan Cell Descriptions (Part 2 of 2) Note (1)
Captures
Drives
Pin Type
Output
Capture
Register
OE
Input
Capture Capture
Register Register
Output
Update
Register
OE
Update
Register
Input
Update
Register
Comments
Dedicated input 0
(3)
Dedicated
0
bidirectional
(open drain) (4)
Dedicated
OUTJ
bidirectional (5)
Dedicated
output (6)
OUTJ
1
PIN_IN N.C. (2) N.C. (2) N.C. (2) PIN_IN drives to
control logic
OEJ
PIN_IN N.C. (2) N.C. (2) N.C. (2) PIN_IN drives to
configuration
control
OEJ
PIN_IN N.C. (2) N.C. (2) N.C. (2) PIN_IN drives to
configuration
control and OUTJ
drives to output
buffer
0
0
N.C. (2) N.C. (2) N.C. (2) OUTJ drives to
output buffer
Notes to Table 9–2:
(1) TDI, TDO, TMS, TCK, all V_CC and GND pin types, VREF, and TEMP_DIODE pins do not have BSCs.
(2) No Connect (N.C.).
(3) This includes pins PLL_ENA, nCONFIG, MSEL0, MSEL1, MSEL2, MSEL3, nCE, VCCSEL, PORSEL, and nIO_PULLUP.
(4) This includes pins CONF_DONE and nSTATUS.
(5) This includes pin DCLK.
(6) This includes pin nCEO.
IEEE Std. 1149.1
BST Operation
Control
Stratix II and Stratix II GX devices implement the following IEEE Std.
1149.1 BST instructions:
■ SAMPLE/PRELOAD instruction mode is used to take snapshot of the
device data without interrupting normal device operations
■ EXTEST instruction mode is used to check external pin connections
between devices
■ BYPASS instruction mode is used when an instruction code
consisting of all ones is loaded into the instruction register
■ IDCODE instruction mode is used to identify the devices in an IEEE
Std. 1149.1 chain
■ USERCODE instruction mode is used to examine the user electronic
signature within the device along an IEEE Std. 1149.1 chain.
Altera Corporation
January 2008
9–7
Stratix II Device Handbook, Volume 2