EP2S90F1020C5 Datasheet, PDF (561/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
128-bit security key is stored in the Stratix II or Stratix II GX device. In
order to successfully configure a Stratix II or Stratix II GX device that has
the design security feature enabled, it must be configured with a
configuration file that was encrypted using the same 128-bit security key.
The security key can be stored in non-volatile memory inside the Stratix II
or Stratix II GX device. This non-volatile memory does not require any
external devices, such as a battery back-up, for storage.
1 When using a serial configuration scheme such as passive serial
(PS) or active serial (AS), configuration time is the same whether
or not the design security feature is enabled. If the fast passive
parallel (FPP) scheme is used with the design security or
decompression feature, a 4× DCLK is required. This results in a
slower configuration time when compared to the configuration
time of an FPGA that has neither the design security, nor
decompression feature enabled. For more information about
this feature, contact Altera Applications group.
f
Remote System Upgrade
Stratix II and Stratix II GX devices feature remote and local update.
For more information about this feature, refer to the Remote System
Upgrades With Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II Device Handbook or the Remote System Upgrades With Stratix II &
Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device
Handbook
Power-On Reset Circuit
The POR circuit keeps the entire system in reset until the power supply
voltage levels have stabilized on power-up. Upon power-up, the device
does not release nSTATUS until V_CCINT, V_CCPD, and V_CCIO of banks 3, 4, 7,
and 8 are above the device’s POR trip point. On power down, V_CCINT is
monitored for brown-out conditions.
The passive serial (PS) mode (MSEL[3,2,1,0] = 0010) and the Fast
passive parallel (FPP) mode (MSEL[3,2,1,0] = 0000) always set
bank 3 to use the lower POR trip point consistent with 1.8- and 1.5-V
signaling, regardless of the VCCSEL setting. For all other configuration
modes, VCCSEL selects the POR trip-point level. Refer to the section
“VCCSEL Pin” on page 7–10 for more details.
In Stratix II devices, a pin-selectable option PORSEL is provided that
allows you to select between a typical POR time setting of 12 ms or
100 ms. In both cases, you can extend the POR time by using an external
component to assert the nSTATUS pin low.
Altera Corporation
January 2008
7–9
Stratix II Device Handbook, Volume 2